Hard decoding is a decoding process that receives a single bit precision codeword of binary input of zeros and/or ones, and tries to correct errors (bit flips). Soft decoding is a decoding process that receives a codeword of binary value as well as an indication about the reliability of the binary value.
FIG. 1 demonstrates a voltage threshold distribution 10 of a triple-level cell (TLC) flash memory. Three page types are defined for the 8-level programming A most significant bit (MSB) page type, which is also called lower page, can be read using thresholds T0 20 and T4 24, a central significance bit (CSB), which is also called middle page, can be read using thresholds T1 21, T3 23 and T5 25, and a lower significance bit (LSB), which is also called upper page, can be read using thresholds T2 22 and T6 26. When the number of errors is sufficiently low a single page read can be used for recovering the original payload data, and this operation is called hard decoding. This is since the input to the decoder is only a logical value of the bit sampled once from the NAND (0/1).
In case the hard decoding fails, a digital signal processing (DSP) unit may perform multiple reads to obtain soft information at the decoder input. From the multiple reads the soft information may be computed, in the form of log-likelihood ratio (LLR), for every codeword bit. The overhead of performing multiple reads for a single codeword may have a significant impact on the overall latency for completing the read transaction. It is therefore desired to minimize the number of reads and attempt decoding with a limited soft information resolution. The example of FIG. 1 shows an erasure sampling (sampling thresholds 11, 12, 13 and 14) where the LSB page is read using only 2 read operations.
The sampling thresholds 11, 12, 13 and 14 are around centers of T2 and T6. The decoder input has 3-levels, which is why this sampling is called 1.5-bit sampling resolution. These 3 input levels may be mapped to LLR values {−1, 0, 1} where bits which have LLR=0 are considered as erasure bits, with equal probability of 0 and 1. In this invention we will describe methods for fast decoding of such input with utilization of hard decoding within soft decoding iterations.
Another voltage threshold distribution 30 is demonstrated in FIG. 2 where a CSB page is sampled with 3 read operations (triplet of read thresholds 31 near T1, triples 32 near T3 and triplet 33 near T5. This may be required when hard decoding fails and 1.5-bit sampling is inefficient. The 3 read operations provides decoder input with 4 sampling levels, which may be mapped to LLR values {−2, −1, 1, 2} where bits which have |LLR|=1 are considered low reliability bits, and the sign of the LLRs is the hard decision input to the decoder.